The use of strained silicon in the manufacturing of semiconductor devices has gained popularity as an effective way to improve conductance in the transistors of such devices. Early efforts at using strained silicon involved embedding silicon-germanium in a silicon layer on opposing sides of a transistor channel region, which caused the silicon atoms in the channel layer to “stretch” in a natural attempt to align with the structure of the silicon-germanium.
The Si—Ge approach is helpful for increasing conductance, which benefits n-type field-effect transistors (FETs, or NFETs), but p-type FETs, or PFETs, did not benefit from the stretched channels. Instead, p-type FETs benefit from the opposite—a more compressed silicon lattice structure in their channel regions. Accordingly, dual stress liner devices have been developed that allow n-type and p-type devices to both enjoy the benefits of strained silicon.
FIG. 1 illustrates an example of a current approach to such dual stress liner devices. On the semiconductor substrate 100, transistor structures such as silicide 101 may be formed, and an isolation structure (e.g., shallow trench isolation 102) may be formed to electrically separate transistors from each other. For example, NFET devices may be formed in a p-well on the left, and PFET may be formed in an n-well on the right. Transistor gate structures 103, such as gate electrodes, gate layers, insulation layers, sidewall spacers, etc. and additional silicide 104 and 105 may be formed as well. Silicide 105 and gate structure may be used as interconnects in regions over the isolation structure 102.
To provide the dual stresses, a tensile stress film 106 may be formed over one region (e.g., an NFET region), while a compressive stress film 107 may be formed over the other region (e.g., a PFET region). Lining up these films at the boundary results in either an overlap (as shown) or a gap (not shown) between the two films. Because leaving a gap would expose the interconnect gate 105 to additional etching when forming contact structures 108a,b, an overlap of the two films is generally preferred.
When forming contact structures 108a,b, careful control over the etching process (e.g., reactive ion etching) is needed to ensure that the structures 108a,b penetrate to the appropriate depth. Since some structures 108a need to penetrate two stress films, while other structures 108b need only penetrate through one stress film, the formation of structures 108a,b is a difficult process.